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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Reverse Polarity Protection on V BAT
In case of a permanently reverse polarity operation, the
output transistors are turned ON (R SD ) to prevent thermal
overloads and no protections are available.
An external diode on VCC is necessary in order to not to
destroy the 35XS3500 in cases of reverse polarity.
In case of negative transients on the V BAT line (per
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Without loads on OUT1:5 terminal, an external
clamp between V BAT and GND is mandatory to avoid
exceeding maximum rating. The maximum external clamp
voltage shall be between the reverse battery condition and ?
-20 V.
Therefore, the device is protected against latch-up with or
without load on OUT outputs.
Loss of Supply Lines
The 35XS3500 is protected against the loss of any supply
line. The detection of the supply line failure is provided inside
provided for RST is set to logic [1]. The SPI pull-up and
pull-down current resistors are available. This fault
condition can be diagnosed with UVF fault in OD13
reporting bit. The previous device configuration is
maintained. No current is conducted from V CC to V BAT .
Loss of V CC (Digital Logic Supply Line)
During loss a of V CC (V CC < V CCUV ) and with wake=1, the
35XS3500 is switched automatically into Fail mode (no
deglich time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when V CC
goes above V CCUV . The device will transit in OFF mode if
VBAT < V BATPOR2 .
LOSS OF V CC AND V BAT
If the external V BAT and V CC supplies are disconnected (or
not within specification: (V CC and V BAT ) < V BATPOR1 ), all SPI
register contents are reset with default values corresponding
to all SPI bits are set to logic [0] and all latched faults are also
reset.
the device itself.
Loss of Ground (GND)
Loss of V BAT
During an under-voltage of V BAT
(V BATPOR1 <V BAT <V BATUV ) and with an active device
(wake=1), the outputs [1-5] are switched off immediately. No
current path exists from V BAT to V CC . The external MOSFET
(OUT6) can be controlled by the SPI if V CC remains and is
above to V CCUV . The fault is reported to the UVF bit (OD13).
To delatch the fault, the under-voltage condition should be
removed and:
? the bit D7 must be rewritten to a logic [1] in Normal
mode. Application of the OCHI window depends on
toggling or not toggling the D7 bit. When the fault is
delatched, the 35XS3500 returns to the configuration it
was just before the failure.
During a loss of ground, the 35XS3500 cannot operate the
loads (the outputs (1:5) are switched OFF), but is not
destroyed by the operating condition. Current limit resistors in
the digital input lines protect the digital supply against
excessive current (1.0 kohm typical). The state of the
external smart power switch controlled by FETOUT is not
guaranteed, and the state of the external smart MOS is
defined with an external termination resistor.
Fatal Mistreatment of Logic I / O Pins
The digital I / Os are protected against fatal mistreatment
Table 17. Logic I / O Plausibility Check
? if the device was in Fail mode, the fault will be delatched
periodically by the Autorestart feature.
In case of V BAT <V BATPOR1 (Power OFF state), the
behavior depends on V CC :
Input / Output
LIMP
(PWM) CLOCK
Signal Check Strategy
Debounce for 10 ms
Frequency range
(bandpass filter)
? all latched faults are reset if V CC < V CCUV ,
? all latched faults are maintained under V CC in nominal
conditions. In case V BAT is disconnected, OUT[1:5]
outputs are OFF. OUT6 output state depends on the
previous SPI configuration. The SPI configuration,
reporting (if V BAT was previously in the nominal voltage
range for at least 35 ? sec), and daisy-chain features are
SPI (MOSI, SCLK, CS) WD, D10 bit internal toggle
In case the LIMP input is set to a logic [1] for a delay longer
than 10 ms typical, the 35XS3500 is switched into Fail mode.
In case of a (PWM) Clock failure, no PWM feature is
provided, and the bit D7 defines the outputs state. In case of
a SPI failure, the 35XS3500 is switched into Fail mode
35XS3500
Analog Integrated Circuit Device Data ?
36
Freescale Semiconductor
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